1. Field of the Invention
The present invention relates generally to a strained silicon channel semiconductor structure. In particular, the present invention relates to a strained silicon channel semiconductor structure with better carrier mobility.
2. Description of the Prior Art
With the trend of miniaturization of semiconductor device dimensions, the scale of the gate, source and drain of a transistor is decreased in accordance with the decrease in critical dimension (CD). Due to the physical limitations of the materials used, the decrease in scale of the gate, source and drain results in the decrease of carriers that determine the magnitude of the current in the transistor element, and this can therefore adversely affect the performance of the transistor. Increasing carrier mobility in order to boost up a metal oxide semiconductor (MOS) transistor is therefore an important topic in the field of current semiconductor techniques.
To boost the carrier mobility, one conventional attempt has been made by forming a strained silicon channel. The strained silicon channel can increase the mobility of an electron (e−) group and a hole (h+) group in the silicon channel without modifying the critical dimension of gate electrode, thereby improving the operation speed of the resulting transistor. This attempt is widely-used in the industry because it may attain better performance for semiconductor devices without complicating the original circuit design or manufacturing process.
In current implementations, one method for forming a strained silicon channel is using selective epitaxial growth (SEG) to grow an epitaxial layer as a stress source in the substrate. The epitaxial layer has the same lattice arrangement but different lattice constant than the silicon substrate. Thus the epitaxial layer may exert a stress on the lattice of the abutted silicon channel region to form a strained silicon channel, thereby attaining the efficacy of increasing carrier mobility.
For example, for the PMOS transistor using holes (h+) as carrier in the channel, a SiGe (silicon-germanium) epitaxial layer may be formed in the source/drain region on the silicon substrate. Due to the lattice constant of SiGe epitaxy being inherently larger than that of Si, the SiGe epitaxial layer will exert a stress on the lattice of abutted silicon channel, thereby forming a compressive strained channel. The band-gap structure of compressive strained channel is advantageous to the transition of holes (h+), thereby increasing the speed of PMOS device.
Similarly, for the NMOS transistor using electrons (e+) as carrier in the channel, a SiC (silicon-carbon) epitaxial layer may be formed in the source/drain region on the silicon substrate. Due to the lattice constant of SiC epitaxy being inherently smaller than that of Si, the SiC epitaxial layer will exert a stress on the lattice of abutted silicon channel, thereby forming a tensile strained channel. The band-gap structure of tensile strained channel is advantageous to the transition of electrons (e+), thereby increasing the speed of NMOS device.
Please refer now to FIG. 1. FIG. 1 is a schematic cross-section view of CMOS transistor structure using the technique of a strained silicon channel in the prior art. As shown in the figure, a conventional CMOS transistor structure 100 includes a PMOS region 102 and a NMOS region 104 spaced-apart by a shallow trench isolation (STI) 105. In addition to the conventional structures such as a gate 105, a source/drain (not shown) and a spacer 108, the PMOS region 102 and NMOS region 104 are also provided with recesses 110 formed on source/drain region in order to provide the space for the filling of stress material (ex. SiGe or SiC) to grow an epitaxial layer 112. The epitaxial layer 112 formed in the recess will exert a stress on a silicon channel region 114 between the source and drain, thereby forming a strained silicon channel and attaining the efficacy of increasing carrier mobility.
The semiconductor industry is still devoted to researching how to improve the carrier mobility and relevant electrical performance in semiconductor devices in order to respond to the even smaller scale of semiconductor devices in the future. Regarding the semiconductor technique based on strained silicon channel, it is still urgent for those skilled in the art to improve the structure thereof for further improving the relevant electrical performance.